Those are good questions. For the ADC, the noise depends on the that mode. In the +/10V mode, the RMS noise is about 0.5 times a single ADC code step (300uV), which isn't much above the theoretical noise limit from the quantization. Often for ADC's, they are spec'd in terms of signal to noise, comparing the noise power to the power of a full-scale sine wave. If you work this out, that works out a little over 93 dB for the SNR. The highest (fractional) noise is when in the +/-1.25V mode, where the RMS is 1.1 times the ADC code step (~40uV) (for hardware rev 3.2 and above) or 1.75 for earlier units. In the case of 1.1, this works out to 86.5 dB. The +/-5V mode has noise of about 0.8 and the +/-2.5V mode of 0.63 relative to the quantization level. The SNR can be expressed as a 'effective number of bits', basically asking how many bits in a noiseless system would give the same noise or SNR. That works out to 15.2 bits in the +/-10V mode and 14.1 in the +/-1.25V mode. And in all these cases, you if don't need the full bandwidth, averaging can increase the SNR / effective number of bits.
The DAC output has RMS noise of about 200uV, which is little under the quantization step size.
The ADC and DACs are each four channels and can be accessed at 1 mega-sample per second. You basically, you can write a DAC value and read an ADC value every 1μs. You can measure the same channel over and over, or switch between them however you'd like. But you cannot read two ADC channels at the same time. The DAC is the same. That said, your code does not need to worry this, and you can write to the DAC 4 times in a row and those DAC write commands will execute in 100ns and then your code can go on to process other things. Behind the scenes, those DAC writes will get parsed out to update the DAC serially as fast as possible, one after the other.
I hope this is helpful. Please let me know if you have any more questions. And I'll add the ADC noise stuff to the specifications page as this really should be there. Thanks,