Hey Ben,

I am curious about the noise you see on the ADCs and DACs. While Arduino and Arduino like controllers (e.g. Teensy) seem to have 16-bit ADCs they usually only state that 12 to 13 bits are usable due to noise levels. Do you have a similar restriction here or are all 16 bits of the ADCs usable with out much extra processing? Similarly what are the noise levels seen on the DACs, is the listed quantization step size just a theoretical value or can it be measured reliably?

Lastly does the qNimble have 4 separate ADCs and 4 separate DACs or is there some form of multiplexing of the inputs/outputs?

I hope to hear from you soon,

Felix

Hi Felix,

Those are good questions. For the ADC, the noise depends on the that mode. In the +/10V mode, the RMS noise is about 0.5 times a single ADC code step (300uV), which isn't much above the theoretical noise limit from the quantization. Often for ADC's, they are spec'd in terms of signal to noise, comparing the noise power to the power of a full-scale sine wave. If you work this out, that works out a little over 93 dB for the SNR. The highest (fractional) noise is when in the +/-1.25V mode, where the RMS is 1.1 times the ADC code step (~40uV) (for hardware rev 3.2 and above) or 1.75 for earlier units. In the case of 1.1, this works out to 86.5 dB. The +/-5V mode has noise of about 0.8 and the +/-2.5V mode of 0.63 relative to the quantization level. The SNR can be expressed as a 'effective number of bits', basically asking how many bits in a noiseless system would give the same noise or SNR. That works out to 15.2 bits in the +/-10V mode and 14.1 in the +/-1.25V mode. And in all these cases, you if don't need the full bandwidth, averaging can increase the SNR / effective number of bits.

The DAC output has RMS noise of about 200uV, which is little under the quantization step size.

The ADC and DACs are each four channels and can be accessed at 1 mega-sample per second. You basically, you can write a DAC value and read an ADC value every 1μs. You can measure the same channel over and over, or switch between them however you'd like. But you cannot read two ADC channels at the same time. The DAC is the same. That said, your code does not need to worry this, and you can write to the DAC 4 times in a row and those DAC write commands will execute in 100ns and then your code can go on to process other things. Behind the scenes, those DAC writes will get parsed out to update the DAC serially as fast as possible, one after the other.

I hope this is helpful. Please let me know if you have any more questions. And I'll add the ADC noise stuff to the specifications page as this really should be there. Thanks,

Ben

7 days later

Hey Ben,

thank you for your quick response to my question. I had another question regarding the rise and fall time of the DAC, i.e. how quickly can the DAC go from 0V to +-10V or any other voltage? Is the rise time linear wrt to the voltage difference (between starting and final voltage)?

Felix

Hi Felix,

The main limitation in the rise/fall time on the DAC output will be the output filter, which has 175 kHz of bandwidth. This response will be linear, in that the response will scale linearly with the voltage change.

Below is an image of two DAC channels generating a 50kHz square wave, offset by 2 us. The yellow trace is a signal going from 4V to -4V while the cyan goes from 1V to -1V. As you can see the shapes is the same in both traces and it takes ~3us to go from min to max.

For larger jumps (>8V delta) you start to see the slew-rate limitation of the DAC become significant and the response is no longer linear and the time to go from min to max increases to about 4us.

Let me know if you need any more details.

Ben

Awesome thank you for your quick response.